1. Field of the Invention
The present invention relates to a metal oxide semiconductor field effect transistor (MOSFET), and more particularly, to a MOSFET and a method of manufacturing the same which is suitable to elevate the current drivability and to improve short channel effects.
2. Discussion of the Related Art
Metal oxide semiconductor (MOS) technology was invented by Fairchild in 1958. It is an innovatory technology for improving the transistor characteristics. The corresponding manufacturing method includes the step of growing a high quality insulating silicon oxide film on the surface of a silicon semiconductor. The invention of the MOS technology accelerated the application of semiconductor-surface devices. As a result, a field effect transistor (FET) was first presented by Texas Instruments in 1962.
MOSFET devices are categorized into p-MOS, n-MOS and CMOS devices. A p-MOS device with easily controllable power consumption and manufacturing process was initially utilized. As the speed of the device becomes more important, an n-MOS device was used because it utilizes electrons with a speed 2.5 times faster than that of holes. A CMOS device has a low power consumption, a complicated manufacturing process, and a low packing density as compared to the p-MOS and n-MOS devices. Presently, a memory part of a device is formed from the n-MOS device, and a periphery circuit part is formed from the CMOS device.
These MOS devices are manufactured by decreasing a channel length for high integration and high speed. Due to the short channel length, a drain depletion region increases and interacts with a channel junction, thereby causing drain induced barrier lowering (DIBL). Further, a leakage current increases because of the punchthrough between the two depletion regions caused by the severe encroachment of the source and drain depletion regions. In addition, as the distance between the source and drain regions decreases, electrons injected from the source region are rapidly accelerated by the high electric field near the pinch-off region of the drain junction, thereby causing hot carrier effects.
The hot carriers are then injected into a gate insulating film and flow toward a substrate, thereby generating a large substrate current. Accordingly, a MOS transistor with a lightly doped drain (LDD) structure was suggested since it reduces the hot carrier effect while maintaining the short channel length.
The LDD structure is a structure in which a self-aligned lightly doped region is located between the channel region and the high concentration impurity region (source/drain regions). The lightly doped region spreads out the high electric field nearby the drain junction so that carriers injected from the source region are not accelerated even though a high voltage is applied, thereby overcoming the instability of current due to the hot carriers.
A method of manufacturing a conventional MOSFET will now be described with reference to FIGS. 1A-1C.
As shown in FIG. 1A, on a semiconductor substrate 1 with a field region and an active region defined, a field oxidation process is performed selectively to form a field oxide film 2 in the field region. Then, a gate oxide film 3, a polysilicon film 4 and a photoresist film (PR.sub.1) are sequentially formed on the active region of the semiconductor substrate 1.
As shown in FIG. 1B, the photoresist film (PR.sub.1) is patterned through exposure and development processes to define a region where a gate electrode is to be formed. Then, using the patterned photoresist film (PR.sub.1) as a mask, the polysilicon film 4 and the gate oxide film 3 are sequentially etched to form a gate electrode 4a. Then, using the gate electrode 4a as the mask, impurity ions with a low concentration are implanted into the substrate on both sides of the gate electrode 4a, thereby forming lightly doped drain (LDD) regions 5.
As shown in FIG. 1C, the photoresist film (PR.sub.1) is removed. Then, an oxide film is formed on the entire surface of the substrate including the gate electrode 4a and etched back to form sidewall spacers 6 on both sides of the gate electrode 4a. Then, using the gate electrode 4a and the sidewall spacers 6 as a mask, impurity ions with a high concentration are implanted into the semiconductor substrate 1 and activated to form high concentration source and drain regions 7.
The conventional MOSFET has the following problems.
First, the conventional MOSFET with the LDD structure forms the lightly doped region between the high concentration impurity region and the gate electrode in order to reduce the electric field near the drain region. This prevents the hot carrier effects to a certain extent. However, since the gate oxide film under the gate electrode is very thin, electric field is generated in the drain region where it interfaces with the gate oxide film. Thus, the generation of carrier trapping in the gate oxide film occurs. Particularly, due to the negative slope caused when the underlying etch-target layer is formed, the gate oxide layer is over-etched to cause the carrier trapping. As a result, the lifetime of the device is reduced.
Secondly, a parasitic capacitance is generated due to the overlap between the gate electrode and the LDD region, thereby decreasing the device speed. Since the current drivability is deteriorated, it is difficult to produce the MOSFET required by the high speed operation.